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DMA Register Access from the Backend
An interface is provided that allows the PCI configuration space and DMA registers to be accessed from the core
backend rather than from the PCI bus. When the backend needs to access these registers, it must arbitrate for control of
the core backend interface using the BE_REQ and BE_GNT handshake signals ( Figure 6-49 to Figure 6-53 on
page 100 ). Once granted, it may access the DMA registers.
cycle
0
1
2
3
clk
be_req
be_gnt
be_address[7:0]
be_write
be_read
mem_data_in[31:0]
ADDR
DATA
Figure 6-49 · DMA Register Single Write Cycle
Writes to the DMA register are accomplished by asserting BE_WRITE, valid address, and valid data at the same time.
Registers can be updated one at a time or in bursts by changing the address and data while keeping BE_WRITE
asserted. If required, BE_WRITE can be deasserted during a burst write. A separate 8-bit address bus, BE_ADDRESS,
is provided. The data input uses the normal MEM_DATA_IN input. Four separate BE_WRITE signals are provided,
one for each byte of the 32-bit wide registers.
cycle
0
1
2
4
5
6
7
8
clk
be_req
be_gnt
be_write
be_read
98
be_address[7:0]
mem_data_out[31:0]
ADDR
DATA
Figure 6-50 · DMA Register Single Read Cycle
v4.0
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